RAM 4.5 BUX II Series Uživatelský manuál stáhnout pdf (Strana 19)

DE1 User Manual

To let users implement and test their IP cores (written in Verilog) without requiring them to

implement complex API/Host control software and memory (SRAM/SDRAM/Flash) controllers,

we provide an integrated control environment consisting of a software controller in C++, a USB

command controller, and a multi-port SRAM/SDRAM/Flash controller.

Figure 3.7. The DE1 Control Panel block diagram.

Users can connect circuits of their own design to one of the User Ports of the SRAM/SDRAM/Flash

controller. Then, they can download binary data into the SRAM/SDRAM/Flash. Once the data is

downloaded to the SDRAM/Flash, users can configure the memory controllers so that their circuits

can read/write the SDRAM/Flash via the User Ports connected.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 55 56

Žádné komentáře

RAM 4.5 BUX II Series Uživatelský manuál Strana 19