RAM 8.0 BUX II Series Uživatelská příručka
Procházejte online nebo si stáhněte Uživatelská příručka pro Audio zesilovače RAM 8.0 BUX II Series. RAM 8.0 BUX II Series User guide Uživatelská příručka
- Strana / 86
- Tabulka s obsahem
- KNIHY
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
Shrnutí obsahu
7 Series FPGAsMemory ResourcesUser GuideUG473 (v1.11) November 12, 2014
10 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Preface: About This Guide• The ALMOST_FULL_OFFSET equation for the 7 s
7 Series FPGAs Memory Resources www.xilinx.com 11UG473 (v1.11) November 12, 2014Chapter 1Block RAM ResourcesSummaryThe block RAM in Xilinx® 7 series F
12 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM Resources• 18, 36, or 72-bit wide block RAM ports
7 Series FPGAs Memory Resources www.xilinx.com 13UG473 (v1.11) November 12, 2014Block RAM Introduction• The A15 pin in the RAMB36E1 should be used for
14 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesEmbedded dual- or single-port RAM module
7 Series FPGAs Memory Resources www.xilinx.com 15UG473 (v1.11) November 12, 2014Synchronous Dual-Port and Single-Port RAMsSynchronous Dual-Port and Si
16 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesRead OperationIn latch mode, the read op
7 Series FPGAs Memory Resources www.xilinx.com 17UG473 (v1.11) November 12, 2014Synchronous Dual-Port and Single-Port RAMsWRITE_FIRST or Transparent M
18 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM Resourcesoutput pipeline register is not used. Th
7 Series FPGAs Memory Resources www.xilinx.com 19UG473 (v1.11) November 12, 2014Additional Block RAM Features in 7 Series Devices• When one port perfo
7 Series FPGAs Memory Resources www.xilinx.com UG473 (v1.11) November 12, 2014The information disclosed to you hereunder (the “Materials”) is provided
20 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesSimple Dual-Port Block RAMEach 18 Kb blo
7 Series FPGAs Memory Resources www.xilinx.com 21UG473 (v1.11) November 12, 2014Additional Block RAM Features in 7 Series DevicesCascadable Block RAMI
22 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM Resourcesenable is not available in the dual-cloc
7 Series FPGAs Memory Resources www.xilinx.com 23UG473 (v1.11) November 12, 2014Block RAM Library Primitivesno longer allowed. The access to uninstant
24 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesTable 1-7 and Table 1-8 show the show th
7 Series FPGAs Memory Resources www.xilinx.com 25UG473 (v1.11) November 12, 2014Block RAM Library PrimitivesREGCEAREGCE Port A output register clock e
26 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesBlock RAM Port SignalsEach block RAM por
7 Series FPGAs Memory Resources www.xilinx.com 27UG473 (v1.11) November 12, 2014Block RAM Port SignalsRegister Enable - REGCEA, REGCE, and REGCEBThe r
28 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesFor cascadable block RAM using the RAMB3
7 Series FPGAs Memory Resources www.xilinx.com 29UG473 (v1.11) November 12, 2014Block RAM Port SignalsData-In Buses - DIADI, DIPADIP, DIBDI, and DIPBD
UG473 (v1.11) November 12, 2014 www.xilinx.com 7 Series FPGAs Memory Resources01/30/2012 1.5 In Table 1-2, removed XC7A8, XC7A15, XC7A30T, and XC7A50T
30 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesInverting Control PinsFor each port, the
7 Series FPGAs Memory Resources www.xilinx.com 31UG473 (v1.11) November 12, 2014Block RAM AttributesBlock RAM AttributesAll attribute code examples ar
32 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesContent Initialization - INITP_xxINITP_x
7 Series FPGAs Memory Resources www.xilinx.com 33UG473 (v1.11) November 12, 2014Block RAM AttributesReset or CE Priority - RSTREG_PRIORITY_[A|B]This a
34 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesMode Selection - RAM_MODEThis attribute
7 Series FPGAs Memory Resources www.xilinx.com 35UG473 (v1.11) November 12, 2014Block RAM Initialization in VHDL or Verilog CodeThe RAMB36_X0Y0 is the
36 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesRAMB18E1 and RAMB36E1 Port Mapping Desig
7 Series FPGAs Memory Resources www.xilinx.com 37UG473 (v1.11) November 12, 2014Block RAM ApplicationsByte-Wide Write EnableThese rules should be cons
38 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesX-Ref Target - Figure 1-11Figure 1-11: B
7 Series FPGAs Memory Resources www.xilinx.com 39UG473 (v1.11) November 12, 2014Block RAM Timing ModelBlock RAM Timing ModelThis section describes the
7 Series FPGAs Memory Resources www.xilinx.com UG473 (v1.11) November 12, 2014
40 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesBlock RAM Timing CharacteristicsThe timi
7 Series FPGAs Memory Resources www.xilinx.com 41UG473 (v1.11) November 12, 2014Block RAM Timing ModelClock Event 1Read OperationDuring a read operati
42 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM ResourcesClock Event 5Disable OperationDeassertin
7 Series FPGAs Memory Resources www.xilinx.com 43UG473 (v1.11) November 12, 2014Stacked Silicon InterconnectStacked Silicon InterconnectThe block RAM
44 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 1: Block RAM Resources
7 Series FPGAs Memory Resources www.xilinx.com 45UG473 (v1.11) November 12, 2014Chapter 2Built-in FIFO SupportOverviewMany FPGA designs use block RAMs
46 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportTwo operating modes affect the reading
7 Series FPGAs Memory Resources www.xilinx.com 47UG473 (v1.11) November 12, 2014Synchronous FIFOSynchronous FIFO ImplementationsTable 2-2 outlines var
48 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportFIFO Architecture: a Top-Level ViewFig
7 Series FPGAs Memory Resources www.xilinx.com 49UG473 (v1.11) November 12, 2014FIFO Port DescriptionsFigure 2-4 shows the FIFO18E1 in FIFO18_36 mode.
7 Series FPGAs Memory Resources www.xilinx.com 5UG473 (v1.11) November 12, 2014Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportREGCE Input Output register clock enab
7 Series FPGAs Memory Resources www.xilinx.com 51UG473 (v1.11) November 12, 2014FIFO OperationsFIFO OperationsResetA reset synchronizer circuit has be
52 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportEmpty FlagThe Empty flag is synchronou
7 Series FPGAs Memory Resources www.xilinx.com 53UG473 (v1.11) November 12, 2014FIFO AttributesFull FlagThe Full flag is synchronous with WRCLK, and i
54 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportTable 2-6 shows how the SRVAL and INIT
7 Series FPGAs Memory Resources www.xilinx.com 55UG473 (v1.11) November 12, 2014FIFO AttributesFIFO Almost Full/Empty Flag Offset RangeThe FIFO data d
56 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportSimilarly, the Almost Empty flag can b
7 Series FPGAs Memory Resources www.xilinx.com 57UG473 (v1.11) November 12, 2014FIFO Timing Models and ParametersClock to Out DelaysTRCKO_DO(2)Clock t
58 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportFIFO Timing CharacteristicsThe various
7 Series FPGAs Memory Resources www.xilinx.com 59UG473 (v1.11) November 12, 2014FIFO Timing Models and ParametersClock Event 1 and Clock Event 3: Writ
6 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Inverting Control Pins . . . . . . . . . . . . . . . . . . . . . . . .
60 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportCase 2: Writing to a Full or Almost Fu
7 Series FPGAs Memory Resources www.xilinx.com 61UG473 (v1.11) November 12, 2014FIFO Timing Models and ParametersClock Event 3: Write Operation and As
62 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO Support• At time TRCKO_DO, after clock event
7 Series FPGAs Memory Resources www.xilinx.com 63UG473 (v1.11) November 12, 2014FIFO Timing Models and Parameters• At time TRCCK_RDEN, before clock ev
64 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportCase 5: Resetting All FlagsFigure 2-10
7 Series FPGAs Memory Resources www.xilinx.com 65UG473 (v1.11) November 12, 2014FIFO Applicationsdata latency of this application is the sum of the in
66 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO SupportConnecting FIFOs in Parallel to Increa
7 Series FPGAs Memory Resources www.xilinx.com 67UG473 (v1.11) November 12, 2014Legal Block RAM and FIFO CombinationsLegal Block RAM and FIFO Combinat
68 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 2: Built-in FIFO Support
7 Series FPGAs Memory Resources www.xilinx.com 69UG473 (v1.11) November 12, 2014Chapter 3Built-in Error CorrectionOverviewThe RAMB36E1 in simple dual-
7 Series FPGAs Memory Resources www.xilinx.com 7UG473 (v1.11) November 12, 2014FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionECC ModesIn the standard ECC mode
7 Series FPGAs Memory Resources www.xilinx.com 71UG473 (v1.11) November 12, 2014Top-Level View of the Block RAM ECC ArchitectureTop-Level View of the
72 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionBlock RAM and FIFO ECC PrimitiveFi
7 Series FPGAs Memory Resources www.xilinx.com 73UG473 (v1.11) November 12, 2014Block RAM and FIFO ECC Port DescriptionsFigure 3-3 shows the FIFO36E1
74 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionRSTREGB Synchronous output registe
7 Series FPGAs Memory Resources www.xilinx.com 75UG473 (v1.11) November 12, 2014Block RAM and FIFO ECC Port DescriptionsTable 3-2 lists and describes
76 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionBlock RAM and FIFO ECC AttributesI
7 Series FPGAs Memory Resources www.xilinx.com 77UG473 (v1.11) November 12, 2014ECC Modes of Operationby you. The FIFO WRADDR and RDADDR addresses are
78 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionX-Ref Target - Figure 3-6Figure 3-
7 Series FPGAs Memory Resources www.xilinx.com 79UG473 (v1.11) November 12, 2014ECC Modes of OperationNote relevant to Figure 3-8:1. Data (DOUT) and c
8 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Standard ECC Read Timing . . . . . . . . . . . . . . . . . . . . . . .
80 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionStandard ECC WriteThis is shown in
7 Series FPGAs Memory Resources www.xilinx.com 81UG473 (v1.11) November 12, 2014ECC Modes of OperationSimilarly, at time T2W and T3W, DI[63:0] = B and
82 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionECC Timing CharacteristicsThe vari
7 Series FPGAs Memory Resources www.xilinx.com 83UG473 (v1.11) November 12, 2014ECC Timing CharacteristicsEncode-Only ECC Write TimingRefer to Figure
84 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error CorrectionBlock RAM ECC Mode Timing Paramete
7 Series FPGAs Memory Resources www.xilinx.com 85UG473 (v1.11) November 12, 2014Creating 8 Parity Bits for a 64-bit WordCreating 8 Parity Bits for a 6
86 www.xilinx.com 7 Series FPGAs Memory ResourcesUG473 (v1.11) November 12, 2014Chapter 3: Built-in Error Correction
7 Series FPGAs Memory Resources www.xilinx.com 9UG473 (v1.11) November 12, 2014PrefaceAbout This GuideXilinx® 7 series FPGAs include three FPGA famili
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