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10 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Preface: About This Guide
The ALMOST_FULL_OFFSET equation for the 7 series FPGAs is changed in the case
where the RDCLK is different from the WRCLK. In this case, the
ALMOST_EMPTY_OFFSET equation is removed because in all cases it follows the
values in Table 2-8.
Changes from Spartan-6 FPGAs
Similar to the Virtex-6 family, the 7 series FPGAs support both 36 Kb and 18 Kb block
RAM configurations (native 36 Kb/18 Kb versus the 18 Kb/9 Kb of the Spartan®-6
FPGAs).
Many key features already available in the Virtex-6
family but not in the Spartan-6
family are included in the 7 series FPGAs implementation:
Dedicated integrated FIFO
Error correction (ECC)
Direct cascade of block RAM
Independent reset control of output latches and registers
Asynchronous set/reset of data outputs
Additional Support Resources
To find additional documentation, see the Xilinx website at:
w
ww.xilinx.com/support/documentation/index
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
w
ww.xilinx.com/support
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